The present invention relates to a semiconductor structure and method and, more particularly, relates to a hybrid semiconductor structure of a nanowire mesh device and a partially depleted semiconductor on insulator device.
Due to their superior electrostatics, gate-all-around nanowire channel field effect transistors (e.g., nanowire FETs) are expected to enable density scaling beyond current planar CMOS technology. In its basic form, a nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which wraps around the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain.